AN-890 P1149.1A Extensions to IEEE-STD-1149.1-1990

Since publication of IEEE-1149.1-1990/ANSI 1, 2, 3, extensions and requests for clarifications have been adopted by the IEEE 1149.1 Working Group. The original standard established a common, industry-wide methodology for the application of scan test access. The rapid acceptance of this standard and use by semiconductor designers, test engineers and systems developers has resulted in questions needing interpretation. Several additional optional instructions were proposed including two that were accepted: CLAMP and HIGHZ. The need for harmonious test integration with existing and proposed scan methodologies resulted in acceptance of a proposal for the subservience of 1149.1’s Test Access Port (TAP) by a higher level static controller. Features of the Original 1149.1 IEEE STD-1149.1/1990 resulted when the users of proprietary scan methods realized that no organization could afford to fully support its own scan technology. The growing use of standard product ICs to implement new systems, meant that the semiconductor industry could not support many proprietary scan access methods. Over a dozen different commercial scan methods were in use in 1985 when the European-originated Joint Test Group (JTAG) began the search for a common standard. This effort evolved into the IEEE sponsored 1149.1. IEEE 1149.1 defines a dedicated 4-pin test access port with an optional fifth pin defined to disable the test logic. Figure 1 shows the basic architecture of the test part. Test patterns are shifted into an IC using Test Data Input (TDI). Simultaneously, the most recent test results can be shifted out using Test Data Output (TDO). A Test Clock (TCK) synchronizes the test logic. Test logic control is provided by Test Mode Select (TMS) which sequences a 16-state Finite State Machine (FSM) in each IC. The test logic in each IC has two major functions: the first to provide a protocol controlled interface between the component and the 1149.1 tester. This function is provided by the TAP Controller. Within the TAP controller is an instruction register that may be loaded from the TDI input. An instruction provides flexibility in test that is limited only by the designers imagination. The second function of the test logic is to provide scan accessible paths to I/O pins using the cells of the boundary-scan register but it also provides access to as many optional internal scan registers as the designer chooses to add. IEEE 1149.1 defines three mandatory instructions and four optional ones. The most common application of 1149.1 has been to verify interconnections and to detect process defects in those interconnections. The three mandatory instructions support this application. The first instruction, SAMPLE/PRELOAD, can be used to preload a test pattern into a scan register. It can sample the system logic state on its system inputs. The sample capability places strict skew requirements between the test clock and the system clock. If these requirements are not met, then only the preload feature will be usable. The second instruction, EXTEST, forces preloaded test vectors, or subsequent vectors onto an IC’s output pins on the falling edge of one TCK edge. After waiting two and one-half TCK clocks, allowing the results to settle, EXTEST captures the results present on its system inputs into the boundary-scan cells. A series of EXTEST vectors is used to isolate interconnection defects. The third mandatory instruction, BYPASS, simply connects TDI to TDO with a one bit shift register called the Bypass register. When testing a cluster of other ICs on a module, test time may be reduced by placing an IC in Bypass mode. During normal system operation, during the Test Logic Reset state, the bypass register may be connected between TDI and TDO. FIGURE 1. Architecture—IEEE Standard Test Access Port and Boundary-Scan Paper first published at NEPCON, 1993.